An Adaptive Distributed Algorithm for Sequential Circuit Test

We describe the parallelization of sequential circuit test generation on an Ethernet-connected network of SUN workstations. We use the observations of the previous work to execute the program in two phases. All processors simultaneously run the test generation program, Gentest. In the rst phase, the fault list is equally divided among processors, each of which derives tests for targets from its list. A time limit is used to abandon the search for a test for hard to detect faults. Any test found is immediately used to simulate all faults, including those assigned to other processors. Due to the sequential nature of the circuit test vectors are not shared, but the fault simulation data are shared among processors. This phase terminates when only hard to detect faults are left. In the second phase, each remaining fault is simultaneously targeted by all processors, which now have di erent initial states of the circuit. The rst processor to nd the test interrupts all others, at which point all processors simultaneously target the next remaining fault. The results show that with this dual strategy, the speedup can be made to increase almost linearly, or sometimes superlinearly, with the number of processors.